The invention generally relates to electronic circuits and more particularly to voltage level shifters. Voltage level shifters have been used in many applications in which a voltage level higher than the one available is needed. For example, an integrated circuit may be required to drive a digital output pin with a logic one voltage level higher than the logic one voltage level used by that chip""s internal logic.
For applications in non-volatile memory circuits, such as flash memory, EPROM, and pro E2PROM, level shifters commonly drive the wordlines (i.e., the pass transistor gates of the memory cells). FIG. 1 shows a standard 6-transistor level shifter 10, which may be used for such application. For memory read operations, the required wordline driver output is usually less than or equal to the digital supply voltage Vdd (1.8 to 5.5V generally). For memory write operations, the required output may be 10V or higher. Therefore, the write operations require a level shifter, such as level shifter 10 in FIG. 1, to drive the word lines. To save chip area, and reduce circuit complexity, the level shifter used during writes is also used during reads, in which the required logic one output voltage usually must be less than or equal to Vdd., In such a case, the output level supply voltage, Vpp, tied to level shifter 10 is simply reduced during reads.
As semiconductor manufacturing processes continue to be scaled down, the thin insulating film of a MOS transistor (i.e., the gate oxide) became too thin to withstand the full high voltage required by some applications. Typically, the maximum gate oxide voltage limit, VgoxMax, is in the 7 to 20 V range, depending on the integrated circuit manufacturing process used. Therefore, level shifter 10 shown in FIG. 1 had to be modified.
FIG. 2 shows a modified level shifter 20 based on the circuit in FIG. 1. In level shifter 20, additional transistors Q2, Q3, Q10, and Q11 were added to limit the maximum voltage seen by any gate oxide in the circuit. This technique is commonly referred to as xe2x80x9ccascading,xe2x80x9d and the added transistors are referred to as xe2x80x9ccascode devices.xe2x80x9d In addition, two more transistors, Q7 and Q8, must be added to discharge nodes that can exceed voltage limitations due to capacitive coupling action. These two modifications double the transistor count of the modified circuit, and very significantly slow down the output switching speed, i.e., they increase the delay between a logic state transition on input A and the resulting output state transition.
To recover the speed, some designs use additional devices to form a second output drive path to drive the output during read operations in which the logic one output voltage must be less than or equal to Vdd. In those designs, the level shifting portion of the circuit formed by transistors Q1 through Q12 in FIG. 2 is used only during write operations in which the logic one output voltage must exceed Vdd , and is disabled otherwise. The second output drive path is composed of transistors Q13, Q14, Q15, and Q16. In this path, Q13 is used as the logic driver, while Q14 is used for mode control. Q15 is a cascode device that protects Q13 and Q14. Finally, Q16 is a discharge device similar in function to Q7 and Q8. Since Q13, Q14, and Q15 are in series, their widths must be relatively large to minimize the state change delay from input A to the output. This second output drive path adds more transistors, and additional control signal requirements since these additional transistors must be protected when the output level supply voltage Vpp exceeds the gate oxide voltage limits.
In FIG. 2, additional control and supply circuits, external to level shifter circuit 20, must be included to control the cascoding (i.e., to drive inputs B, C, and D) and to control the separate driver path (i.e., drive supply voltage Vrr and input E), thus increasing the total chip area and circuit complexity. Since the level shifting portion of the circuit is disabled during read operations, the modified circuit in FIG. 2 is incapable of driving voltages above Vdd for read operations. Due to the cascading devices, the level shifting portion is too slow to use for fast reads. This prohibits the use of this circuit as a memory wordline driver for applications where, e.g., wordline voltage boosting techniques are needed to allow fast memory read operations at low digital supply voltage Vdd.
Therefore, there is a need for an improved voltage level shifter that is capable of driving level shifted voltages fast enough for reads and with gate oxide protection for write operations, for applications in memory circuits, without increasing the circuit""s size or complexity.
The present invention provides an improved voltage level shifter circuit. The circuit comprises an output stage that is configured to generate a desired level shifted voltage in response to a digital input; a voltage level shifter, operably coupled to the output stage, that is configured to receive a logic value and drive the output stage to cause the output stage to generate the desired level shifted voltage; an input stage, operably coupled to the level shifter, that is configured to receive the digital input and provide the logic value and a protection signal to the level shifter; and means, operably coupled to the input and output stages and the level shifter, for receiving the protection signal for providing voltage protection to the output stage and the level shifter when the desired level shifted voltage is greater than a maximum gate oxide voltage limit.
According to one aspect of the invention, when a digital supply voltage applied to the level shifter is less than a reference level and the desired level shifted voltage (e.g., at logic 1 voltage) is an elevated digital level voltage equal to the reference level, the output stage is further configured to receive an output stage supply voltage at the reference level that is less than the maximum gate oxide voltage limit. The elevated digital level voltage is equal to the output stage supply voltage.
According to another aspect of the invention, when the desired level shifted voltage is greater than the maximum gate oxide voltage limit, the output stage is further configured to receive an output stage supply voltage that is greater than the maximum gate oxide voltage limit. The desired level shifted voltage is equal to the output stage supply voltage.
According to a future aspect of the invention, when the desired level shifted voltage is less than a digital supply voltage applied to the level shifter, the output stage is further configured to receive an output stage supply voltage that is less than the digital supply voltage, and the desired level shifted voltage is equal to the output stage supply voltage.
According to a further aspect of the invention, when the desired level shifted voltage is equal to a digital supply voltage applied to the level shifter, the output stage is further configured to receive an output stage supply voltage that is equal to the digital supply voltage, and the desired level shifted voltage is equal to the output stage supply voltage.
The circuit of the invention is about 50% smaller than the conventional level shifter shown in FIG. 2, with fewer input control and supply lines, thus reducing circuit area and control complexity. Furthermore, only one regulated cascode voltage input is need, reducing implementation complexity.
In the circuit of the invention, the transient switching current is reduced due to the separation of a level shifting portion of the circuit from the output stage that is used to drive a load. Moreover, the propagation delay from the digital input to the level shifted output is reduced due to the removal of series cascode devices in the level shifting portion of the circuit (i.e. transistors Q2, Q3, Q10, and Q11 in FIG. 2 are no longer needed).